LL TIM APIs listing for migration

There are a few API changes in the LL layer. This page lists only the modified LL APIs. Others not listed here are unchanged between HAL1 and HAL2.

LL TIM constants

HAL1

series

HAL2

LL_TIM_TIM16_TI1_RMP_RTC_WK

g4, g0

LL_TIM_TIM16_TI1_RTC_WKUP

LL_TIM_TIM16_TI1_RMP_RTC

u5, l4

LL_TIM_TIM16_TI1_RTC_WKUP

LL_TIM_TIM16_TI1_RMP_MSIS_4

u5

LL_TIM_TIM16_TI1_MSIS_DIV4

LL_TIM_TIM16_TI1_RMP_MSIS_1024

u5

LL_TIM_TIM16_TI1_MSIS_DIV1024

LL_TIM_TIM16_TI1_RMP_HSI_256

u5

LL_TIM_TIM16_TI1_HSI_DIV256

LL_TIM_TIM16_TI1_RMP_HSE_32

l4, g4

LL_TIM_TIM16_TI1_HSE_DIV32

LL_TIM_TIM17_TI1_RMP_RTC

u5

LL_TIM_TIM17_TI1_RTC_WKUP

LL_TIM_TIM17_TI1_RMP_MSIS_4

u5

LL_TIM_TIM17_TI1_MSIS_DIV4

LL_TIM_TIM17_TI1_RMP_MSIS_1024

u5

LL_TIM_TIM17_TI1_MSIS_DIV1024

LL_TIM_TIM17_TI1_RMP_HSI_256

u5

LL_TIM_TIM17_TI1_HSI_DIV256

LL_TIM_TIM15_TI2_RMP_TIM4

h5

LL_TIM_TIM15_TI2_TIM4_CH2

LL_TIM_TIM15_ENCODERMODE_TIM4

l4

Not implemented yet in HAL2.

LL_TIM_TIM15_ENCODERMODE_TIM3

l4

Not implemented yet in HAL2.

LL_TIM_TIM15_ENCODERMODE_TIM2

l4

Not implemented yet in HAL2.

LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION

l4

Not implemented yet in HAL2.

LL_TIM_TIM14_TI1_RMP_RTC_CLK

c0, g0

LL_TIM_TIM14_TI1_RTC

LL_TIM_TIM17_TI1_RMP_RTC_WK

g4

LL_TIM_TIM17_TI1_RTC_WKUP

LL_TIM_TIM15_TI2_RMP_TIM3

h5

LL_TIM_TIM15_TI2_TIM3_CH2

LL_TIM_TIM15_TI2_RMP_TIM2

h5

LL_TIM_TIM15_TI2_TIM2_CH2

LL_TIM_TIM15_TI1_RMP_TIM4

h5

LL_TIM_TIM15_TI1_TIM4_CH1

LL_TIM_TIM15_TI1_RMP_TIM3

h5

LL_TIM_TIM15_TI1_TIM3_CH1

LL_TIM_TIM15_TI1_RMP_TIM2

h5

LL_TIM_TIM15_TI1_TIM2_CH1

LL_TIM_TIM1_ETR_ADC1_RMP_AWD2

l4

Not implemented yet in HAL2.

LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO

f4

Not implemented yet in HAL2.

LL_TIM_TIM1_ITR2_RMP_LPTIM

f4

Not implemented yet in HAL2.

LL_TIM_TIM1_ETR_ADC3_RMP_NC

l4

Not implemented yet in HAL2.

LL_TIM_TIM1_ETR_ADC3_RMP_AWD3

l4

Not implemented yet in HAL2.

LL_TIM_TIM1_ETR_ADC3_RMP_AWD2

l4

Not implemented yet in HAL2.

LL_TIM_TIM1_ETR_ADC3_RMP_AWD1

l4

Not implemented yet in HAL2.

LL_TIM_TIM1_ETR_ADC1_RMP_NC

l4

Not implemented yet in HAL2.

LL_TIM_OCMODE_RETRIG_OPM1

u5, h5, c0, l4, g4, g0

LL_TIM_OCMODE_RETRIGERRABLE_OPM1

LL_TIM_ONEPULSEMODE_SINGLE

u5, h5, c0, l4, g4, g0, f4

Removed /Replaced by LL function LL_TIM_EnableOnePulseMode

LL_TIM_ONEPULSEMODE_REPETITIVE

u5, h5, c0, l4, g4, g0, f4

Removed /Not need it in HAL2 since it’s the default configuration.

LL_TIM_OCMODE_ACTIVE

u5, h5, c0, l4, g4, g0, f4

LL_TIM_OCMODE_ACTIVE_ON_MATCH

LL_TIM_OCIDLESTATE_HIGH

u5, h5, c0, l4, g4, g0, f4

LL_TIM_OCIDLESTATE_SET

LL_TIM_LPTIM_REMAP_MASK

f4

Not implemented yet in HAL2.

LL_TIM_OCIDLESTATE_LOW

u5, h5, c0, l4, g4, g0, f4

LL_TIM_OCIDLESTATE_RESET

LL_TIM_OCMODE_INACTIVE

u5, h5, c0, l4, g4, g0, f4

LL_TIM_OCMODE_INACTIVE_ON_MATCH

LL_TIM_TIM12_TI1_RMP_HSI_1024

h5

LL_TIM_TIM12_TI1_HSI_DIV1024

LL_TIM_TIM11_TI1_RMP_GPIO2

f4

Not implemented yet in HAL2.

LL_TIM_TIM11_TI1_RMP_GPIO1

f4

Not implemented yet in HAL2.

LL_TIM_TIM12_TI1_RMP_CSI_128

h5

Not implemented yet in HAL2.

LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER

u5, h5, c0, l4, g4, g0

LL_TIM_SLAVEMODE_COMBINED_RESET_TRIGGER

LL_TIM_SLAVEMODE_COMBINED_GATEDRESET

u5, h5, g4

LL_TIM_SLAVEMODE_COMBINED_GATED_RESET

LL_TIM_PWPRSC_X8

u5, h5, g4

LL_TIM_PWPRSC_DIV8

LL_TIM_PWPRSC_X4

u5, h5, g4

LL_TIM_PWPRSC_DIV4

LL_TIM_PWPRSC_X32

u5, h5, g4

LL_TIM_PWPRSC_DIV32

LL_TIM_PWPRSC_X2

u5, h5, g4

LL_TIM_PWPRSC_DIV2

LL_TIM_PWPRSC_X16

u5, h5, g4

LL_TIM_PWPRSC_DIV16

LL_TIM_PWPRSC_X128

u5, h5, g4

LL_TIM_PWPRSC_DIV128

LL_TIM_PWPRSC_X1

u5, h5, g4

LL_TIM_PWPRSC_DIV1

LL_TIM_PWPRSC_X64

u5, h5, g4

LL_TIM_PWPRSC_DIV64

LL_TIM_SMSPS_INDEX

u5, h5, g4

LL_TIM_SLAVE_MODE_PRELOAD_INDEX

LL_TIM_SMSPS_TIMUPDATE

u5, h5, g4

LL_TIM_SLAVE_MODE_PRELOAD_UPDATE

LL_TIM_TIM5_TI4_RMP_RTC

f4

LL_TIM_TIM5_TI1_RTC_WKUP

LL_TIM_TIM8_ETR_ADC2_RMP_AWD3

l4

Not implemented yet in HAL2.

LL_TIM_TIM8_ETR_ADC2_RMP_AWD2

l4

Not implemented yet in HAL2.

LL_TIM_TIM8_ETR_ADC2_RMP_AWD1

l4

Not implemented yet in HAL2.

LL_TIM_TIM8_ETR_ADC2_RMP_NC

l4

Not implemented yet in HAL2.

LL_TIM_TIM5_TI1_RMP_RTC_WK

g4

LL_TIM_TIM5_TI1_RTC_WKUP

LL_TIM_TIM5_TI1_RMP_RTC

u5

LL_TIM_TIM5_TI1_RTC_WKUP

LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO

f4

Not implemented yet in HAL2.

LL_TIM_TIM5_ITR1_RMP_LPTIM

f4

Not implemented yet in HAL2.

LL_TIM_TIM8_ETR_ADC3_RMP_AWD1

l4

Not implemented yet in HAL2.

LL_TIM_TIM8_ETR_ADC3_RMP_AWD3

l4

Not implemented yet in HAL2.

LL_TIM_TRGO_OC4REF

u5, h5, c0, l4, g4, g0, f4

LL_TIM_TRGO_OC4

LL_TIM_TRGO_OC3REF

u5, h5, c0, l4, g4, g0, f4

LL_TIM_TRGO_OC3

LL_TIM_TRGO_OC2REF

u5, h5, c0, l4, g4, g0, f4

LL_TIM_TRGO_OC2

LL_TIM_TRGO_OC1REF

u5, h5, c0, l4, g4, g0, f4

LL_TIM_TRGO_OC1

LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO

f4

Not implemented yet in HAL2.

LL_TIM_TIM9_ITR1_RMP_LPTIM

f4

Not implemented yet in HAL2.

LL_TIM_TIM8_ETR_ADC3_RMP_NC

l4

Not implemented yet in HAL2.

LL_TIM_TIM8_ETR_ADC3_RMP_AWD2

l4

Not implemented yet in HAL2.

LL_TIM_TRGO2_OC4_RISINGFALLING

u5, h5, c0, l4, g4, g0

LL_TIM_TRGO2_OC4_RISING_FALLING

LL_TIM_TRGO2_OC6_RISINGFALLING

u5, h5, c0, l4, g4, g0

LL_TIM_TRGO2_OC6_RISING_FALLING

LL_TIM_TIM2_TI4_RMP_COMP1_COMP2

l4

Not implemented yet in HAL2.

LL_TIM_TIM2_TI2_RMP_HSI_1024

h5

LL_TIM_TIM12_TI1_HSI_DIV1024

LL_TIM_TIM2_TI2_RMP_CSI_128

h5

Not implemented yet in HAL2.

LL_TIM_TIM2_ITR1_RMP_USB_SOF

l4

Not implemented yet in HAL2.

LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO

l4, f4

Not implemented yet in HAL2.

LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF

f4

Not implemented yet in HAL2.

LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF

l4, f4

Not implemented yet in HAL2.

LL_TIM_TIM2_ITR1_RMP_NONE

l4

Not implemented yet in HAL2.

LL_TIM_TIM2_ITR1_RMP_ETH_PTP

f4

Not implemented yet in HAL2.

LL_TIM_TIM2_ETR_RMP_GPIO

l4

Not implemented yet in HAL2.

LL_TIM_TIM2_TI1_RMP_TIM3_TI1

h5

LL_TIM_TIM2_TI1_TIM3_CH1

LL_TIM_TIM2_TI1_RMP_RTC

h5

LL_TIM_TIM2_TI1_RTC_WKUP

LL_TIM_TIM3_TI1_RMP_TIM2_TI1

h5

LL_TIM_TIM3_TI1_TIM2_CH1

LL_TIM_TIM3_TI1_RMP_COMP1_COMP2

l4

Not implemented yet in HAL2.

LL_TIM_TIM3_TI2_RMP_CSI_128

h5

Not implemented yet in HAL2.

LL_TIM_TIM3_TI2_RMP_HSI_1024

h5

LL_TIM_TIM12_TI1_HSI_DIV1024

LL_TIM_OCMODE_RETRIG_OPM2

u5, h5, c0, l4, g4, g0

LL_TIM_OCMODE_RETRIGERRABLE_OPM2

LL_TIM_DMA_TRIGGER

u5, h5

LL_TIM_DMABURST_TRGI

LL_TIM_DMA_COM

u5, h5

LL_TIM_DMABURST_COM

LL_TIM_DMA_CC4

u5, h5

LL_TIM_DMABURST_CC4

LL_TIM_DMA_CC3

u5, h5

LL_TIM_DMABURST_CC3

LL_TIM_DMA_CC2

u5, h5

LL_TIM_DMABURST_CC2

LL_TIM_DMA_CC1

u5, h5

LL_TIM_DMABURST_CC1

LL_TIM_DMA_UPDATE

u5, h5

LL_TIM_DMABURST_UPD

LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1

u5, h5, g4

LL_TIM_CLK_ENCODER_CLK_PLUS_X1

LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2

u5, h5, g4

LL_TIM_CLK_ENCODER_CLK_PLUS_X2

LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12

u5, h5, g4

LL_TIM_CLK_ENCODER_DIR_CLK_X1_TI12

LL_TIM_ETRSOURCE_LEGACY

l4

Not implemented yet in HAL2.

LL_TIM_ENCODERMODE_X4_TI12

u5, h5, c0, l4, g4, g0, f4

LL_TIM_CLK_ENCODER_X4_TI12

LL_TIM_ENCODERMODE_X2_TI2

u5, h5, c0, l4, g4, g0, f4

LL_TIM_CLK_ENCODER_X2_TI2

LL_TIM_ENCODERMODE_X2_TI1

u5, h5, c0, l4, g4, g0, f4

LL_TIM_CLK_ENCODER_X2_TI1

LL_TIM_ENCODERMODE_X1_TI2

u5, h5, g4

LL_TIM_CLK_ENCODER_X1_TI2

LL_TIM_ENCODERMODE_X1_TI1

u5, h5, g4

LL_TIM_CLK_ENCODER_X1_TI1

LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2

u5, h5, g4

LL_TIM_CLK_ENCODER_DIR_CLK_X2

LL_TIM_DMABURST_BASEADDR_OR

h5

Not implemented yet in HAL2.

LL_TIM_DMABURST_BASEADDR_OR2

h5

Not implemented yet in HAL2.

LL_TIM_DMABURST_BASEADDR_OR3

h5

Not implemented yet in HAL2.

LL_TIM_BKIN_SOURCE_PLAY1

h5

Not implemented yet in HAL2.

LL_TIM_BKIN_SOURCE_DF1BK

l4

Not implemented yet in HAL2.

LL_TIM_BKIN_SOURCE_BKCOMP4

g4

LL_TIM_TIM1_BRK_COMP4_OUT

LL_TIM_BKIN_SOURCE_BKCOMP3

g4, g0

LL_TIM_TIM1_BRK_COMP3_OUT

LL_TIM_BKIN_SOURCE_BKCOMP2

u5, h5, l4, g4, g0

LL_TIM_TIM1_BRK_COMP2_OUT

LL_TIM_BKIN_SOURCE_BKCOMP1

u5, h5, l4, g4, g0

LL_TIM_TIM1_BRK_COMP1_OUT

LL_TIM_BKIN_POLARITY_LOW

u5, h5, c0, l4, g4, g0

LL_TIM_BREAK_INPUT_SRC_INVERTED

LL_TIM_BKIN_POLARITY_HIGH

u5, h5, c0, l4, g4, g0

LL_TIM_BREAK_INPUT_SRC_NONINVERTED

LL_TIM_BKIN_SOURCE_BKCOMP5

g4

LL_TIM_TIM1_BRK_COMP5_OUT

LL_TIM_ACTIVEINPUT_INDIRECTTI

u5, h5, c0, l4, g4, g0, f4

LL_TIM_ACTIVEINPUT_INDIRECT

LL_TIM_ACTIVEINPUT_DIRECTTI

u5, h5, c0, l4, g4, g0, f4

LL_TIM_ACTIVEINPUT_DIRECT

LL_TIM_BKIN_SOURCE_BKCOMP6

g4

LL_TIM_TIM1_BRK_COMP6_OUT

LL_TIM_BKIN_SOURCE_BKCOMP7

g4

LL_TIM_TIM1_BRK_COMP7_OUT

LL_TIM_BKIN_SOURCE_BKIN

u5, h5, c0, l4, g4, g0

LL_TIM_TIM1_BRK_GPIO

LL_TIM_CLOCKSOURCE_EXT_MODE1

u5, h5, c0, l4, g4, g0, f4

LL_TIM_CLK_EXTERNAL_MODE1

LL_TIM_CLOCKSOURCE_EXT_MODE2

u5, h5, c0, l4, g4, g0, f4

LL_TIM_CLK_EXTERNAL_MODE2

LL_TIM_CLOCKSOURCE_INTERNAL

u5, h5, c0, l4, g4, g0, f4

LL_TIM_CLK_INTERNAL

LL_TIM_CCUPDATESOURCE_COMG_ONLY

u5, h5, c0, l4, g4, g0, f4

LL_TIM_CCUPDATESOURCE_SOFTWARE

LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI

u5, h5, c0, l4, g4, g0, f4

LL_TIM_CCUPDATESOURCE_SOFTWARE_AND_TRIGGER

LL_TIM_CCDMAREQUEST_UPDATE

u5, h5, c0, l4, g4, g0, f4

LL_TIM_CCDMAREQUEST_UPD

LL_TIM_BREAK_INPUT_BKIN2

u5, h5, c0, l4, g4, g0

LL_TIM_BREAK_INPUT_2

LL_TIM_BREAK_INPUT_BKIN

u5, h5, c0, l4, g4, g0

LL_TIM_BREAK_INPUT_1

LL_TIM_GROUPCH5_OC1REFC

u5, h5, c0, l4, g4, g0

LL_TIM_GROUPCH5_AND_OC1REFC

LL_TIM_HSE_32_REQUEST

g4

Not implemented yet in HAL2.

LL_TIM_GROUPCH5_OC2REFC

u5, h5, c0, l4, g4, g0

LL_TIM_GROUPCH5_AND_OC2REFC

LL_TIM_GROUPCH5_OC3REFC

u5, h5, c0, l4, g4, g0

LL_TIM_GROUPCH5_AND_OC3REFC

LL_TIM_HSE_32_NOT_REQUEST

g4

Not implemented yet in HAL2.

LL_TIM_IC_POLARITY_BOTHEDGE

u5, h5, c0, l4, g4, g0, f4

LL_TIM_IC_POLARITY_RISING_FALLING

LL_TIM_ETRSOURCE_COMP3

c0

Not implemented yet in HAL2.

LL_TIM_ETRSOURCE_COMP1

l4, g0

Not implemented yet in HAL2.

LL_TIM_ETRSOURCE_COMP2

l4, g0

Not implemented yet in HAL2.

LL_TIM_ETRSOURCE_ADC1_AWD1

c0, g0

Not implemented yet in HAL2.

LL_TIM_ETRSOURCE_ADC1_AWD2

c0, g0

Not implemented yet in HAL2.

LL_TIM_ETRSOURCE_ADC1_AWD3

c0, g0

Not implemented yet in HAL2.

LL_TIM_ETRSOURCE_GPIO

c0, g0

Not implemented yet in HAL2.

LL_TIM_ETRSOURCE_LSE

c0, g0

Not implemented yet in HAL2.

LL_TIM_ETRSOURCE_MCO

c0, g0

Not implemented yet in HAL2.

LL_TIM_ETRSOURCE_MCO2

c0, g0

Not implemented yet in HAL2.

LL_TIM_TIM11_TI1_RMP_HSE_RTC

u5

LL_TIM_TIM11_TI1_HSE_RTC

LL_TIM_TIM11_TI1_RMP_SPDIFRX

u5

Not implemented yet in HAL2.

LL_TIM_TIM12_TI2_RMP_COMP2

u5

LL_TIM_TIM12_TI2_COMP2_OUT

LL_TIM_TIM13_TI1_RMP_COMP1

u5

LL_TIM_TIM13_TI1_COMP1_OUT

LL_TIM_TIM13_TI1_RMP_COMP2

u5

LL_TIM_TIM13_TI1_COMP2_OUT

LL_TIM_TIM14_TI1_RMP_COMP1

u5

LL_TIM_TIM14_TI1_COMP1_OUT

LL_TIM_TIM14_TI1_RMP_COMP2

u5

LL_TIM_TIM14_TI1_COMP2_OUT

LL_TIM_TIM15_TI1_RMP_CSI_128

u5

Not implemented yet in HAL2.

LL_TIM_TIM15_TI1_RMP_RCC_CSI

u5

Not implemented yet in HAL2.

LL_TIM_TIM15_TI1_RMP_RCC_LSE

u5

Not implemented yet in HAL2.

LL_TIM_TIM15_TI1_RMP_RCC_MCO2

u5

LL_TIM_TIM15_TI1_MCO2

LL_TIM_TIM15_TI2_RMP_COMP1

u5

LL_TIM_TIM15_TI2_COMP1_OUT

LL_TIM_TIM15_TI2_RMP_COMP7

u5

LL_TIM_TIM15_TI2_COMP7_OUT

LL_TIM_TIM16_TI1_RMP_COMP2

u5

LL_TIM_TIM16_TI1_COMP2_OUT

LL_TIM_TIM16_TI1_RMP_MSI

u5

LL_TIM_TIM16_TI1_MSI

LL_TIM_TIM16_TI1_RMP_RCC_LSE

u5

Not implemented yet in HAL2.

LL_TIM_TIM16_TI1_RMP_RCC_LSI

u5

Not implemented yet in HAL2.

LL_TIM_TIM16_TI1_RMP_WKUP_IT

u5

Not implemented yet in HAL2.

LL_TIM_TIM17_TI1_RMP_COMP2

u5

LL_TIM_TIM17_TI1_COMP2_OUT

LL_TIM_TIM17_TI1_RMP_HSI48

u5

Not implemented yet in HAL2.

LL_TIM_TIM17_TI1_RMP_MSI

u5

LL_TIM_TIM17_TI1_MSI

LL_TIM_TIM17_TI1_RMP_RCC_HSE1MHZ

u5

Not implemented yet in HAL2.

LL_TIM_TIM17_TI1_RMP_RCC_MCO1

u5

LL_TIM_TIM17_TI1_MCO1

LL_TIM_TIM1_ETR_ADC1_RMP_AWD1

u5

Not implemented yet in HAL2.

LL_TIM_TIM1_ETR_ADC1_RMP_AWD3

u5

Not implemented yet in HAL2.

LL_TIM_TIM1_TI3_RMP_COMP3

u5

LL_TIM_TIM1_TI3_COMP3_OUT

LL_TIM_TIM20_ETRSOURCE_ADC5_AWD1

u5

LL_TIM_TIM20_ETR_IN_ADC5_AWD1

LL_TIM_TIM20_ETRSOURCE_ADC5_AWD2

u5

LL_TIM_TIM20_ETR_IN_ADC5_AWD2

LL_TIM_TIM20_ETRSOURCE_ADC5_AWD3

u5

LL_TIM_TIM20_ETR_IN_ADC5_AWD3

LL_TIM_TIM23_ETRSOURCE_COMP1

u5

LL_TIM_TIM23_ETR_IN_COMP1_OUT

LL_TIM_TIM23_ETRSOURCE_COMP2

u5

LL_TIM_TIM23_ETR_IN_COMP2_OUT

LL_TIM_TIM23_ETRSOURCE_GPIO

u5

LL_TIM_TIM23_ETR_IN_GPIO

LL_TIM_TIM23_TI4_RMP_COMP1

u5

LL_TIM_TIM23_TI4_COMP1_OUT

LL_TIM_TIM23_TI4_RMP_COMP1_COMP2

u5

Not implemented yet in HAL2.

LL_TIM_TIM23_TI4_RMP_COMP2

u5

LL_TIM_TIM23_TI4_COMP2_OUT

LL_TIM_TIM23_TI4_RMP_GPIO

u5

LL_TIM_TIM23_TI4_GPIO

LL_TIM_TIM24_ETRSOURCE_GPIO

u5

LL_TIM_TIM24_ETR_IN_GPIO

LL_TIM_TIM24_ETRSOURCE_SAI1_FSA

u5

LL_TIM_TIM24_ETR_IN_SAI1_FSA

LL_TIM_TIM24_ETRSOURCE_SAI1_FSB

u5

LL_TIM_TIM24_ETR_IN_SAI1_FSB

LL_TIM_TIM24_ETRSOURCE_SAI4_FSA

u5

LL_TIM_TIM24_ETR_IN_SAI4_FSA

LL_TIM_TIM24_ETRSOURCE_SAI4_FSB

u5

LL_TIM_TIM24_ETR_IN_SAI4_FSB

LL_TIM_TIM24_TI1_RMP_CAN_RTP

u5

LL_TIM_TIM24_TI1_CAN_RTP

LL_TIM_TIM24_TI1_RMP_CAN_SOC

u5

LL_TIM_TIM24_TI1_CAN_SOC

LL_TIM_TIM24_TI1_RMP_CAN_TMP

u5

LL_TIM_TIM24_TI1_CAN_TMP

LL_TIM_TIM24_TI1_RMP_GPIO

u5

LL_TIM_TIM24_TI1_GPIO

LL_TIM_TIM2_ETRSOURCE_PLAY1_OUT0

u5

Not implemented yet in HAL2.

LL_TIM_TIM2_ETRSOURCE_RCC_LSE

u5

Not implemented yet in HAL2.

LL_TIM_TIM2_ETR_RMP_LSE

u5

Not implemented yet in HAL2.

LL_TIM_TIM2_TI1_RMP_COMP4

u5

LL_TIM_TIM2_TI1_COMP4_OUT.

LL_TIM_TIM2_TI1_RMP_LSE

u5

LL_TIM_TIM2_TI1_LSE.

LL_TIM_TIM2_TI1_RMP_LSI

u5

LL_TIM_TIM2_TI1_LSI.

LL_TIM_TIM2_TI1_RMP_PLAY1_OUT3

u5

Not implemented yet in HAL2.

LL_TIM_TIM2_TI2_RMP_COMP3

u5

LL_TIM_TIM2_TI2_COMP3_OUT

LL_TIM_TIM2_TI3_RMP_COMP3

u5

LL_TIM_TIM2_TI3_COMP3_OUT

LL_TIM_TIM2_TI3_RMP_COMP4

u5

LL_TIM_TIM2_TI3_COMP4_OUT

LL_TIM_TIM3_ETRSOURCE_PLAY1_OUT0

u5

Not implemented yet in HAL2.

LL_TIM_TIM3_TI1_RMP_COMP4

u5

LL_TIM_TIM3_TI1_COMP4_OUT

LL_TIM_TIM3_TI1_RMP_COMP6

u5

LL_TIM_TIM3_TI1_COMP6_OUT

LL_TIM_TIM3_TI1_RMP_HSE_1MHZ

u5

Not implemented yet in HAL2.

LL_TIM_TIM3_TI1_RMP_MCO1

u5

LL_TIM_TIM3_TI1_MCO1

LL_TIM_TIM3_TI1_RMP_PLAY1_OUT3

u5

Not implemented yet in HAL2.

LL_TIM_TIM3_TI2_RMP_COMP3

u5

LL_TIM_TIM3_TI2_COMP3_OUT.

LL_TIM_TIM3_TI2_RMP_COMP5

u5

LL_TIM_TIM3_TI2_COMP5_OUT.

LL_TIM_TIM3_TI2_RMP_COMP7

u5

LL_TIM_TIM3_TI2_COMP7_OUT.

LL_TIM_TIM3_TI2_RMP_MCO2

u5

LL_TIM_TIM3_TI2_MCO2

LL_TIM_TIM3_TI3_RMP_COMP3

u5

LL_TIM_TIM3_TI3_COMP3_OUT.

LL_TIM_TIM4_TI1_RMP_COMP4

u5

LL_TIM_TIM4_TI1_COMP4_OUT.

LL_TIM_TIM4_TI1_RMP_COMP6

u5

LL_TIM_TIM4_TI1_COMP6_OUT.

LL_TIM_TIM4_TI2_RMP_COMP3

u5

LL_TIM_TIM4_TI2_COMP3_OUT.

LL_TIM_TIM4_TI2_RMP_COMP5

u5

LL_TIM_TIM4_TI2_COMP5_OUT.

LL_TIM_TIM4_TI2_RMP_COMP7

u5

LL_TIM_TIM4_TI2_COMP7_OUT.

LL_TIM_TIM4_TI3_RMP_COMP3

u5

LL_TIM_TIM4_TI3_COMP3_OUT.

LL_TIM_TIM4_TI3_RMP_COMP5

u5

LL_TIM_TIM4_TI3_COMP5_OUT.

LL_TIM_TIM4_TI4_RMP_COMP6

u5

LL_TIM_TIM4_TI4_COMP6_OUT.

LL_TIM_TIM5_ETRSOURCE_SAI4_FSA

u5

LL_TIM_TIM24_ETR_IN_SAI4_FSA

LL_TIM_TIM5_ETRSOURCE_SAI4_FSB

u5

LL_TIM_TIM24_ETR_IN_SAI4_FSB

LL_TIM_TIM5_TI1_RMP_CAN_RTP

u5

Not implemented yet in HAL2.

LL_TIM_TIM5_TI1_RMP_CAN_TMP

u5

Not implemented yet in HAL2.

LL_TIM_TIM5_TI1_RMP_COMP4

u5

LL_TIM_TIM5_TI1_COMP4_OUT.

LL_TIM_TIM5_TI1_RMP_COMP6

u5

LL_TIM_TIM5_TI1_COMP6_OUT.

LL_TIM_TIM5_TI2_RMP_COMP3

u5

LL_TIM_TIM5_TI2_COMP3_OUT.

LL_TIM_TIM5_TI2_RMP_COMP5

u5

LL_TIM_TIM5_TI2_COMP5_OUT.

LL_TIM_TIM5_TI2_RMP_COMP7

u5

LL_TIM_TIM5_TI2_COMP7_OUT.

LL_TIM_TIM5_TI4_RMP_LSE

u5

LL_TIM_TIM5_TI4_LSE.

LL_TIM_TIM5_TI4_RMP_LSI

u5

LL_TIM_TIM5_TI4_LSI.

LL TIM macros

HAL1

series

HAL2

__LL_TIM_CALC_DELAY

u5, h5, c0, l4, g4, g0, f4

LL_TIM_CALC_DELAY

__LL_TIM_CALC_ARR

u5, h5, c0, l4, g4, g0, f4

LL_TIM_CALC_ARR

LL_TIM_ReadReg

u5, h5, c0, l4, g4, g0, f4

LL_TIM_READ_REG

__LL_TIM_CALC_DELAY_DITHER

u5, h5, g4

LL_TIM_CALC_DELAY_DITHER

__LL_TIM_CALC_PSC

u5, h5, c0, l4, g4, g0, f4

LL_TIM_CALC_PSC

__LL_TIM_CALC_PULSE

u5, h5, c0, l4, g4, g0, f4

LL_TIM_CALC_PULSE

__LL_TIM_CALC_DEADTIME

u5, h5, c0, l4, g4, g0, f4

LL_TIM_CALC_DEADTIME

__LL_TIM_CALC_PULSE_DITHER

u5, h5, g4

LL_TIM_CALC_PULSE_DITHER

__LL_TIM_GET_ICPSC_RATIO

u5, h5, c0, l4, g4, g0, f4

LL_TIM_GET_ICPSC_RATIO

LL_TIM_WriteReg

u5, h5, c0, l4, g4, g0, f4

LL_TIM_WRITE_REG

__LL_TIM_GETFLAG_UIFCPY

u5, h5, c0, l4, g4, g0

LL_TIM_GETFLAG_UIFCPY

__LL_TIM_CALC_ARR_DITHER

u5, h5, g4

LL_TIM_CALC_ARR_DITHER

LL TIM structures

HAL1

series

HAL2

LL_TIM_OC_InitTypeDef

u5, h5, c0, l4, g4, g0, f4

Removed

LL_TIM_IC_InitTypeDef

u5, h5, c0, l4, g4, g0, f4

Removed

LL_TIM_BDTR_InitTypeDef

u5, h5, c0, l4, g4, g0, f4

Removed

LL_TIM_HALLSENSOR_InitTypeDef

u5, h5, c0, l4, g4, g0, f4

Removed

LL_TIM_InitTypeDef

u5, h5, c0, l4, g4, g0, f4

Removed

LL_TIM_ENCODER_InitTypeDef

u5, h5, c0, l4, g4, g0, f4

Removed

LL TIM functions

HAL1

series

HAL2

LL_TIM_OC_Init

u5, h5, c0, l4, g4, g0, f4

Removed / New sequence changes

LL_TIM_OC_StructInit

u5, h5, c0, l4, g4, g0, f4

Removed / New sequence changes

LL_TIM_IC_StructInit

u5, h5, c0, l4, g4, g0, f4

Removed / New sequence changes

LL_TIM_BDTR_Init

u5, h5, c0, l4, g4, g0, f4

Removed / New sequence changes

LL_TIM_BDTR_StructInit

u5, h5, c0, l4, g4, g0, f4

Removed / New sequence changes

LL_TIM_IsEnabledRTCPRE

h5

Not implemented yet in HAL2.

LL_TIM_Init

u5, h5, c0, l4, g4, g0, f4

Removed / New sequence changes

LL_TIM_ENCODER_StructInit

u5, h5, c0, l4, g4, g0, f4

Removed / New sequence changes

LL_TIM_ENCODER_Init

u5, h5, c0, l4, g4, g0, f4

Removed / New sequence changes

LL_TIM_DisableRTCPRE

h5

Not implemented yet in HAL2.

LL_TIM_StructInit

u5, h5, c0, l4, g4, g0, f4

Removed / New sequence changes

LL_TIM_EnableRTCPRE

h5

Not implemented yet in HAL2.

LL_TIM_HALLSENSOR_Init

u5, h5, c0, l4, g4, g0, f4

Removed / New sequence changes

LL_TIM_GetOnePulseMode

u5, h5, c0, l4, g4, g0, f4

Removed / New sequence changes

LL_TIM_HALLSENSOR_StructInit

u5, h5, c0, l4, g4, g0, f4

Removed / New sequence changes

LL_TIM_ConfigIDX

u5, h5, g4

LL_TIM_ConfigEncoderIndex

LL_TIM_GetIndexblanking

u5, h5

LL_TIM_GetIndexBlanking

LL_TIM_SetIndexblanking

u5, h5

LL_TIM_SetIndexBlanking

LL_TIM_ConfigBRK

l4, h7

LL_TIM_ConfigBRK (with or without break input mode selection)

LL_TIM_ConfigBRK2

l4, h7

LL_TIM_ConfigBRK2 (with or without break input mode selection)

LL_TIM_IC_Init

u5, h5, c0, l4, g4, g0, f4

Removed / New sequence changes

LL_TIM_SetEncoderMode

u5, h5, c0, l4, g4, g0, f4

LL_TIM_SetClockSource

LL_TIM_SetOnePulseMode

u5, h5, c0, l4, g4, g0, f4

LL_TIM_EnableOnePulseMode /LL_TIM_DisableOnePulseMode

LL_TIM_DeInit

u5, h5, c0, l4, g4, g0, f4

Removed / New usage changes